Aspects of semiconductor fabrication have focused on developing integrated circuits including high-speed and large-capacity analog capacitors formed in a logic circuit region. In order to obtain high-speed capacitors, it may be necessary to lower the resistance of electrodes of the capacitors and decrease frequency dependency. Further, in order to obtain large-capacity capacitors, it may be necessary to decrease the thickness of a capacitor dielectric layer and incorporate a high-dielectric dielectric layer or increase the overall area of the capacitor.
A high-capacity capacitor may include a polysilicon-insulator-polysilicon (PIP) structure in which an upper electrode and a lower electrode may be used as conductive polysilicon. This structure, however, may present problems such as a decrease in capacitance due to oxidization at the interface of the upper electrode and the lower electrode. Such oxidation may produce an insulating thin film and a native oxide layer at the interface.
In order to eliminate such oxidation at the interface, capacitors having a metal-insulator-metal (MIM) structure. A MIM type capacitor may have low resistivity and does not exhibit parasitic capacitance due to depletion therein. Accordingly, MIM capacitors may be used as high-performance semiconductor devices requiring a high Q value.
As illustrated in example FIG. 1, a logic process for a semiconductor device that may include interlayer insulating layer 20 formed on and/or over silicon semiconductor substrate 10. Metal layer 30 for a lower electrode, dielectric layer 40, metal layer 50 for an upper electrode, and hard mask layer 60 may be sequentially formed on and/or over interlayer insulating layer 20. Dielectric layer 40 may be composed of silicon nitride or an oxide. Hard mask film 60 may serve as a hard mask in a subsequent upper electrode etch process and a subsequent via hole etch process. Hard mask film 60 may be composed of silicon nitride, nitride, oxide nitride or the like.
As illustrated in example FIG. 2, a photolithographic process may be performed to form first photoresist pattern 70 on which the upper electrode of the MIM capacitor will be patterned on the hard mask layer 60. The hard mask layer 60 is selectively etched by a reactive ion etch process employing plasma, thus forming a hard mask film pattern 61. The metal layer 50 for the upper electrode is etched by a dry etch process employing plasma by using the hard mask layer pattern 61 as an etch mask, thus forming an upper electrode 51 of the capacitor.
As illustrated in example FIGS. 3 and 4, after first photoresist pattern 70 is removed, a photolithographic process may be performed to form second photoresist pattern 80 on which the lower electrode of the MIM capacitor will be patterned. Dielectric layer 40 may be selectively etched using a reactive ion etch (RIE) process employing plasma to form dielectric layer pattern 41.
Metal layer 30 for the lower electrode may be etched using a dry etch process employing plasma by using dielectric layer pattern 41 as an etch mask to form lower electrode 31 of the capacitor. Second photoresist pattern 80 may then be removed.
As illustrated in example FIG. 5, capping nitride layer 90 composed of SiN may be formed on and/or over semiconductor substrate 10 in which lower electrode 31 is formed. Capping nitride layer 90 may serve to prevent the diffusion of lower electrode 31. Inter-metal insulating layer 91 may be formed on and/or over capping nitride layer 90. The resulting surface may be polished using a chemical mechanical polishing (CMP) process.
Thereafter, portions of inter-metal insulating layer 91 may be selectively etched. Via holes through which the uppermost surface of lower electrode 31 and upper electrode 51 are exposed may be formed using a photolithographic process. A conductive layer may be buried in the via holes to form contact plugs 92. A metal layer may be deposited on and/or over inter-metal insulating layer 91 and then patterned through known processes. Thus, metal lines 93 connected to lower electrode 31 and upper electrode 51, respectively, may be formed through contact plugs 92.
However, such an MIM capacitor structure can be disadvantageous due to the fabrication complexity that requires formation of several mask and etching processes. This, in turn, increases overall production time and production costs.
Even still, in order to increase the capacity of such an MIM capacitor structure, it may be necessary to increase the overall area of the MIM capacitor. This may become difficult to achieve due to limitations in reducing the thickness of the dielectric layer.